Senior Physical Design Verification Layout Engineer
פורסם 21 במאי · 0 מועמדים
התפקיד במילים פשוטות
המהנדס יהיה אחראי על תכנון ומיקום פיזי של שבבים, ויבטיח אינטגרציה בתוך המבנים החדשניים של החברה. הוא יריץ, יתקן ויאשר זרימות אימות פיזיקליות על פני מספר פרויקטים, ויבצע הטמעה, תכנון ואופטימיזציה של פריסה פיזית.
- B.SC./ M.SC. in Electrical Engineering
- 5+ years of hands-on layout experience
- strong background in Physical Verification methodology, including ERC, LVS and DRC
- in-depth knowledge of advanced silicon process technologies
- familiarity with physical build EDA tools, including Synopsys and Cadence
- experience in Linux environments
- TCL, Python, shell scripting abilities
- experience with data collection and analysis
- understanding of the chip and die verification process
חולץ מתיאור המשרה · מתעדכן אוטומטית
למי זה מתאים
התפקיד מתאים למהנדסים בעלי תואר ראשון או שני בהנדסת חשמל, עם לפחות 5 שנות ניסיון מעשי בפריסה ורקע חזק במתודולוגיית אימות פיזיקלי. הוא פחות מתאים למועמדים ללא ניסיון קודם או ידע בכלי EDA.
תיאור המשרה המלא
המשרה המקורית · נשמר לעיוןNVIDIA is looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
What You'll Be Doing
You will be responsible for chip floorplan and pin placement, ensuring integration within our innovative builds.
We expect you to run, debug, and approve Physical Verification flows across multiple projects, ensuring strict adherence to our high standards.
You will perform physical layout implementation, planning and optimization, contributing to the development of our groundbreaking chips.
What We Need To See
B.SC./ M.SC. in Electrical Engineering
You should have at least 5+ years of hands-on layout experience, demonstrating your proven expertise.
A strong background in Physical Verification methodology, including ERC, LVS and DRC, is necessary.
In-depth knowledge of advanced silicon process technologies.
Familiarity with physical build EDA tools, including Synopsys and Cadence.
A great teammate who thrives in a collaborative environment.
AI tools orientation or alternatively a desire to learn.
Ways To Stand Out From The Crowd
Experience in Linux environments.
TCL, Python, shell scripting abilities.
Experience with data collection and analysis
Understanding of the chip and die verification process
NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry!
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שאלות על המשרה
- המשרה לא ציינה שכר. אנחנו מציגים שכר רק כשהמעסיק מפרסם אותו.
- B.SC./ M.SC. in Electrical Engineering, 5+ years of hands-on layout experience, strong background in Physical Verification methodology, including ERC, LVS and DRC, in-depth knowledge of advanced silicon process technologies, familiarity with physical build EDA tools, including Synopsys and Cadence